The present invention relates to digital memory systems, and more specifically, to synchronous memory systems.
As the operational frequencies of digital computing systems continue to increase, it has become increasingly necessary to use synchronous memory systems instead of the slower asynchronous memory systems. In synchronous memory systems, data is sent between a master device and one or more memory devices in the form of data packets which travel in parallel with, and must maintain precise timing relationships with, a system clock signal.
Because synchronous memory systems impose tight timing relationships between the clock and data signals, the memory interface circuits in the memory devices of the synchronous memory system generally require clock recovery and alignment circuits such as phase locked loops (PLLs) or delay locked loops (DLLs). One drawback of these clock recovery and alignment circuits, however, is that they typically operate effectively only over a limited range of frequencies. For example, a PLL may not be able to lock to the system""s clock frequency if the frequency is either too low or too high. Additionally, the performance of these clock recovery and alignment circuits is degraded due to conditions such as temperature, supply voltage, speed binning codes, process, dimensions (i.e. length) of the memory bus, etc.
It is an object of this invention to provide for an adjustable synchronous memory system.
It is a further object of this invention to provide for a synchronous memory system that uses frequency information to improve the performance of the circuits at the system clock frequency.
It is a further object of this invention to provide for a synchronous memory system that uses system parameters to improve the performance of the circuits at the system clock frequency.
The present invention is a method for adjusting the performance of a synchronous memory system. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.